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mos integrated circuit m m m m pd31172 v rc 4172 tm companion chip for v r 4121 tm document no. u14388ej2v0ds00 (2nd edition) date published may 2000 n cp(k) printed in japan data sheet the mark shows major revised points. description the m pd31172 (commercial name: v rc 4172) is a companion chip designed for necs m pd30121 microprocessor (commercial name: v r 4121). the v rc 4172 has the following functions available on chip: a usb host controller, an ieee1284 parallel controller, a 16550 serial controller, a ps/2 controller, general-purpose ports (gpio), programmable chip select (pcs), and a pwm controller (a duty modulated light pulse generation function for lcd backlighting). the v rc 4172 can be directly connected to the v r 4121, allowing a reduction in the man-hours required for development of a windows? ce system. detailed function descriptions are provided in the following users manual. be sure to read it before designing. v rc 4172 users manual (u14386e) features ? directly connectable to v r 4121 ? on-chip usb host controller ? usb ports: 2 ? compliant with the usb openhci specifications, release 1.0 ? communicates with usb device asynchronously with host cpu ? full-speed (12 mbps) and low-speed (1.5 mbps) modes supported ? system clock: 48 mhz ? on-chip ps/2 controller ? on-chip ieee1284 parallel controller ? on-chip 16550 serial controller ? general-purpose ports (gpio): 24 ? on-chip pwm controller ? duty modulated light pulse generation function for lcd backlighting ? internal maximum operating frequency: 48 mhz ? power supply voltage: v dd = 3.3 v 0.3 v ? package: 208-pin plastic fbga applications battery-driven portable information devices peripheral devices for pcs, etc. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
data sheet u14388ej2v0ds00 2 m m m m pd31172 ordering information part number package internal maximum operating frequency m pd31172f1-48-fn 208-pin plastic fbga (15 15) 48 mhz pin configuration 208-pin plastic fbga (15 15) m pd31172f1-48-fn bottom view top view a b c d e f g h j k l m n p r t u u t r p n m l k j h g f e d c b a index mark 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
data sheet u14388ej2v0ds00 3 m m m m pd31172 symbol name symbol name symbol name symbol name a1 gnd c2 gnd e3 cd3 j15 gnd a2 autofeed# c3 strobe# e4 cd7 j16 uucas# a3 pe c4 ack# e14 gnd j17 romcs3# a4 init# c5 error# e15 ppon1 k1 gpio14 a5 iochrdy c6 ad6 e16 oci2 k2 gpio10 a6 ad19 c7 ad7 e17 usbrst# k3 gpio7 a7 ad20 c8 ad8 f1 gpio22 k4 gpio3 a8 ad21 c9 v dd f2 gpio18 k14 excs3# a9 ad22 c10 ad9 f3 cd2 k15 excs0# a10 ad23 c11 ad10 f4 cd6 k16 scas# a11 ad24 c12 ad11 f14 sclk k17 sras# a12 reserved note 1 c13 lcdbak f15 ppon2 l1 gpio13 a13 reserved note 1 c14 smi# f16 lcas# l2 gpio9 a14 dp1 c15 usbint# f17 mras0# l3 gpio6 a15 dn2 c16 gnd g1 gpio21 l4 gpio2 a16 dp2 c17 rd# g2 gpio17 l14 excs4# a17 lcdrdy d1 gnd g3 cd1 l15 excs1# b1 ps2clk d2 selectin# g4 cd5 l16 reserved (0) note 2 b2 v dd d3 dir1284 g14 reserved note 1 l17 gnd b3 v dd d4 ps2int g15 reserved note 1 m1 gpio12 b4 busy d5 select g16 ucas# m2 gpio8 b5 gnd d6 ad0 g17 mras1# m3 gpio5 b6 ad12 d7 ad1 h1 gpio20 m4 gpio1 b7 ad13 d8 ad2 h2 gpio16 m14 excs5# b8 ad14 d9 gnd h3 cd0 m15 excs2# b9 ad15 d10 ad3 h4 cd4 m16 reserved (0) note 2 b10 ad16 d11 ad4 h14 reserved note 1 m17 cke b11 ad17 d12 ad5 h15 arbclksel n1 reset b12 ad18 d13 v dd h16 ulcas# n2 busrq0# b13 gnd d14 ien h17 romcs2# n3 gpio4 b14 dn1 d15 wake j1 gpio15 n4 gpio0 b15 v dd d16 oci1 j2 gpio11 n14 gnd b16 gnd d17 lcdcs# j3 v dd n15 dsr# b17 wr# e1 gpio23 j4 gnd n16 rxd c1 ps2data e2 gpio19 j14 v dd n17 ri# notes 1. either leave pins a12, a13, g14, g15, and h14 open, or input 0 v. 2. always input 0 v to pins l16 and m16. remark # indicates active low.
data sheet u14388ej2v0ds00 4 m m m m pd31172 symbol name symbol name symbol name symbol name p1 holdrq# r1 holdak# t1 busclk u1 iocs16# p2 busak0# r2 gnd t2 gnd u2 irq p3 busrq1# r3 busak1# t3 v dd u3 ior# p4 gnd r4 data23 t4 v dd u4 iow# p5 data31 r5 data22 t5 data15 u5 gnd p6 data30 r6 v dd t6 data14 u6 data7 p7 data29 r7 data21 t7 gnd u7 data6 p8 data28 r8 data20 t8 data13 u8 data5 p9 v dd r9 gnd t9 data12 u9 data4 p10 data27 r10 data19 t10 data11 u10 data3 p11 data26 r11 data18 t11 data10 u11 data2 p12 data25 r12 v dd t12 gnd u12 data1 p13 data24 r13 data17 t13 data9 u13 data0 p14 clkout48m r14 data16 t14 data8 u14 gnd p15 dcd# r15 cts# t15 v dd u15 dtr# p16 txd r16 gnd t16 v dd u16 rts# p17 intrp r17 xout48m t17 xin48m u17 gnd remark # indicates active low.
data sheet u14388ej2v0ds00 5 m m m m pd31172 pin identification ack#: acknowledge mras (0:1)#: dram row address strobe ad (0:24): address bus oci (1:2): over current interrupt arbclksel: arbitration clock select pe: paper end autofeed#: autofeed ppon (1:2): port power on busak (0:1)#: bus acknowledge ps2clk: ps2 clock busclk: system bus clock ps2data: ps2 data busrq (0:1)#: bus request ps2int: ps2 interrupt busy: busy rd#: read cd (0:7): centronics data reset: reset cke: clock enable ri#: ring indicator clkout48m: clock out of 48 mhz romcs (2:3)#: rom chip select cts#: clear to send rts#: request to send data (0:31): data bus rxd: receive data dcd#: data carrier detect column address strobe for dir1284: direction of 1284 scas#: sdram dn (1:2): usb d - sclk: sdram clock dp (1:2): usb d+ select: select dsr#: data set ready selectin#: select in dtr#: data terminal ready smi#: usb system interrupt error#: error row address strobe for excs (0:5)#: external cs sras#: sdram gnd: ground strobe#: strobe gpio (0:23): general purpose i/o txd: transmit data holdak#: hold acknowledge ucas#: upper column address strobe holdrq#: hold request lower byte of upper column ien: usb input enable ulcas#: address strobe init# initialize usbint#: usb interrupt intrp: interrupt usbrst#: usb reset iochrdy: i/o channel ready upper byte of upper column iocs16#: io chip select 16 uucas#: address strobe ior#: i/o read v dd : power supply voltage iow#: i/o write wake: wake up interrupt irq: i/o request wr#: write lcas#: lower column address strobe xin48m: clock in of 48 mhz lcdbak: lcd back light xout48m: clock out of 48 mhz lcdcs#: lcd chip select lcdrdy: lcd ready remark # indicates active low.
data sheet u14388ej2v0ds00 6 m m m m pd31172 internal block diagram and external block connection example . . . . . . . . 48 mhz sdram dram controller ieee1284 parallel controller 2 ports rs-232-c driver pci bus controller internal pci bus system bus usb host controller (openhci 1.0) v rc 4172 16550 serial controller lcd backlight ps/2 controller pwm controller pcs (6 bits) gpio (24 bits) pmu icu v r 4121
data sheet u14388ej2v0ds00 7 m m m m pd31172 contents 1. pin functions................................................................................................................ ................... 8 1.1 pin function list ........................................................................................................... ............................ 8 1.2 special status pins ......................................................................................................... ........................ 11 1.3 external processing of pins and drive capacity.............................................................................. .... 13 1.4 recommended connection of unused pins....................................................................................... .. 15 2. electrical specifications................................................................................................... ... 16 3. package drawing ............................................................................................................. .......... 38 4. recommended soldering conditions................................................................................ 39
data sheet u14388ej2v0ds00 8 m m m m pd31172 1. pin functions 1.1 pin function list (1) system bus interface signals signal name i/o function sclk i/o this is the sdram operating clock. ad (0:24) i/o these form a 25-bit address bus. data (0:31) i/o these form a 32-bit data bus. lcdcs# input this is the lcd chip select signal. this signal becomes active when the v r 4121 accesses the lcd using the ad or data bus. rd# i/o output: this signal becomes active when the v rc 4172 accesses sdram. input: this signal becomes active when the v r 4121 reads data from the v rc 4172s pci host bridge. wr# i/o output: this signal becomes active when the v rc 4172 writes data to sdram. input: this signal becomes active when the v r 4121 writes data to the v rc 4172s pci host bridge. lcdrdy output this is the lcd ready signal. this signal becomes active when a state is entered whereby the v rc 4172 can acknowledge an access to the lcd area from the v r 4121. romcs (2:3)# i/o this is an sdram chip select signal. cke i/o this is the sdram clock enable signal. uucas# i/o this is an sdram dqm signal. this signal controls the i/o buffers for the data (24:31) pins. ulcas# i/o this is an sdram dqm signal. this signal controls the i/o buffers for the data (16:23) pins. mras (0:1)# i/o this is an sdram chip select signal. ucas# i/o this is an sdram dqm signal. this signal controls the i/o buffers for the data (8:15) pins. lcas# i/o this is an sdram dqm signal. this signal controls the i/o buffers for the data (0:7) pins. ior# input this is the system bus i/o r ead signal. this signal becomes active when any resource except the usb inside the v rc 4172 is accessed. iow# input this is the system bus i/o write si gnal. this signal becomes active when any resource except the usb inside the v rc 4172 is accessed. reset input this is the system bus reset si gnal. iocs16# output this is the dynamic bus-sizing request signal. iochrdy output this is the system bus r eady signal. holdrq# output this is the system bus access right r equest signal. holdak# input this is the system bus access enable signal. sras# i/o this is the sdram ras signal. scas# i/o this is the sdram cas signal. busrq (0:1)# input this is a signal input from the external bus master requesting access to the system bus. busak (0:1)# output this is a signal output to the external bus master permitting access to the system bus. intrp output this is an interrupt request signal from the 16550 serial controller or the ieee1284 parallel controller. irq output this is an interrupt request signal from the general-purpose ports (gpio (0:23)) or the ieee1284 parallel controller. usbint# output this is an interrupt request signal from the usb host controller. ps2int output this is an interrupt request signal from the ps/2 controller. busclk input this is the system bus clock. arbclksel input this is a clock select signal for arbitrating the system bus (controls the holdrq# si gnal) (1: internal clock used, 0: busclk used)
data sheet u14388ej2v0ds00 9 m m m m pd31172 (2) usb interface signals signal name i/o function dp (1:2) i/o this is the positive data signal. dn (1:2) i/o this is the negative data signal. ppon (1:2) output this is the usb route-hub-port power supply control signal. oci (1:2) input this is the usb route-hub-port over-current status signal. make this signal active when the current flowing through the vbus line of the usb exceeds the reference value. ien input this is the usb buffer input enable signal. make this signal active when the input signal to the usb port is validated. wake output this is a wakeup interrupt request signal. smi# output this is a system interrupt r equest signal. usbrst# input this is the reset signal for the usb clock. (3) ieee1284 interface signals signal name i/o function cd (0:7) i/o these are data signals strobe# i/o this is the data strobe signal. ack# i/o this is the acknowledge signal. busy i/o this is the busy signal. pe i/o this is the paper-end signal. select i/o this is the select signal. autofeed# i/o this is the autofeed signal. slectin# i/o this is the select input signal. error# i/o this is the fault signal. init# i/o this is the initialization signal. dir1284 output this signal outputs the transfer direction status. (4) rs-232-c interface signals signal name i/o function rxd input this is the receive data signal. cts# input this is the transmit enable signal. dsr# input this is the data set ready signal. txd output this is the transmit data signal. rts# output this is the transmit request signal. dtr# output this is the terminal equipment ready signal. dcd# input this is the carrier detection signal. ri# input this is the call display signal.
data sheet u14388ej2v0ds00 10 m m m m pd31172 (5) ps/2 interface signals signal name i/o function ps2clk i/o this is the ps/2 clock signal. ps2data i/o this is the ps/2 data signal. (6) general-purpose port signals signal name i/o function gpio (0:23) i/o these are general-purpose i/o signals. (7) general-purpose chip select signals signal name i/o function excs (0:5)# output these are general-purpose chip select signals. (8) lcd interface signals signal name i/o function lcdbak output these are signals for controlling the lcd backlighting. (9) clock signals signal name i/o function xin48m input this is the 48 mhz oscillator input pin. connect to one side of a crystal resonator. xout48m output this is the 48 mhz oscillator output pin. connect to the other side of the crystal resonator. clkout48m output this is the 48 mhz clock output for the fir of the v r 4121.
data sheet u14388ej2v0ds00 11 m m m m pd31172 1.2 special status pins (1/2) signal name after reset when holdak# = 1 sclk hi-z hi-z ad (0:24) hi-z hi-z data (0:31) hi-z hi-z lcdcs# -- rd# hi-z hi-z wr# hi-z hi-z lcdrdy hi-z hi-z romcs (2:3)# hi-z hi-z cke hi-z hi-z uucas# hi-z hi-z ulcas# hi-z hi-z mras (0:1)# hi-z hi-z ucas# hi-z hi-z lcas# hi-z hi-z ior# -- iow# -- reset -- iocs16# hi-z hi-z iochrdy hi-z hi-z holdrq# 1 1 holdak# -- sras# hi-z hi-z scas# hi-z hi-z busrq (0:1)# -- busak (0:1)# 1 normal operation intrp 0 normal operation irq 0 normal operation usbint# 1 normal operation ps2int 0 normal operation busclk -- arbclksel -- dp (1:2) 1 normal operation dn (1:2) 0 normal operation ppon (1:2) 0 normal operation oci (1:2) -- ien -- wake 0 normal operation remark 0: low level, 1: high level, hi-z: high impedance
data sheet u14388ej2v0ds00 12 m m m m pd31172 (2/2) signal name after reset when holdak# = 1 smi# 1 normal operation usbrst# -- cd (0:7) hi-z normal operation strobe# hi-z normal operation ack# hi-z normal operation busy hi-z normal operation pe hi-z normal operation select hi-z normal operation autofeed# hi-z normal operation selectin# hi-z normal operation error# hi-z normal operation init# hi-z normal operation dir1284 0 normal operation rxd -- cts# -- dsr# -- txd 1 normal operation rts# 1 normal operation dtr# 1 normal operation dcd# -- ri# -- ps2clk 0 normal operation ps2data hi-z normal operation gpio (0:23) hi-z normal operation excs (0:5)# 1 normal operation lcdbak 0 normal operation clkout48m 1 normal operation remark 0: low level, 1: high level, hi-z: high impedance
data sheet u14388ej2v0ds00 13 m m m m pd31172 1.3 external processing of pins and drive capacity when using the v rc 4172, process the pins externally, as shown in the table below. (1/2) signal name external processing drive capacity tolerance sclk - 80 pf 3 v ad (0:24) - 80 pf 3 v data (0:31) - 80 pf 3 v lcdcs# pull up - 3 v rd# pull up note 1 80 pf 3 v wr# pull up note 1 80 pf 3 v lcdrdy pull up 40 pf 3 v romcs (2:3)# pull up 80 pf 3 v cke pull down 80 pf 3 v uucas# pull up note 1 80 pf 3 v ulcas# pull up note 1 80 pf 3 v mras (0:1)# pull up note 1 80 pf 3 v ucas# pull up note 1 80 pf 3 v lcas# pull up note 1 80 pf 3 v ior# pull up note 1 - 3 v iow# pull up note 1 - 3 v reset -- 3 v iocs16# pull up 40 pf 3 v iochrdy pull up 40 pf 3 v holdrq# - 40 pf 3 v holdak# pull up - 3 v sras# pull up note 1 80 pf 3 v scas# pull up note 1 80 pf 3 v busrq (0:1)# -- 3 v busak (0:1)# - 40 pf 3 v intrp - 40 pf 3 v irq - 40 pf 3 v usbint# - 40 pf 3 v ps2int - 40 pf 3 v busclk -- 3 v arbclksel -- 3 v dp (1:2) - note 2 5 v dn (1:2) - note 2 5 v notes 1. the same specification has been made for these pins in the v r 4121. if these pins have been processed in the v r 4121, there is no need to perform this processing in the v rc 4172. 2. in full-speed mode: 50 pf, in low-speed mode: 350 pf remark there is no need to perform external processing if no particular external processing has been specified ( - ).
data sheet u14388ej2v0ds00 14 m m m m pd31172 (2/2) signal name external processing drive capacity tolerance ppon (1:2) - 40 pf 3 v oci (1:2) -- 3 v ien -- 3 v wake - 40 pf 3 v smi# - 40 pf 3 v usbrst# -- 3 v cd (0:7) - 40 pf 3 v strobe# pull up 40 pf 3 v ack# pull up 40 pf 3 v busy pull down 40 pf 3 v pe pull down 40 pf 3 v select pull down 40 pf 3 v autofeed# pull up 40 pf 3 v selectin# pull up 40 pf 3 v error# pull up 40 pf 3 v init# pull up 40 pf 3 v dir1284 - 40 pf 3 v rxd -- 3 v cts# -- 3 v dsr# -- 3 v txd - 40 pf 3 v rts# - 40 pf 3 v dtr# - 40 pf 3 v dcd# -- 3 v ri# -- 3 v ps2clk pull up 40 pf 5 v ps2data pull up 40 pf 5 v gpio (0:23) pull up/pull down 40 pf 3 v excs (0:5)# - 40 pf 3 v lcdbak - 40 pf 3 v clkout48m - 40 pf 3 v remark there is no need to perform external processing if no particular external processing has been specified ( - ).
data sheet u14388ej2v0ds00 15 m m m m pd31172 1.4 recommended connection of unused pins connect unused pins as shown in the table below. signal name recommended connection signal name recommended connection sclk pull up ppon (1:2) leave open ad (0:24) - oci (1:2) pull down data (0:31) - ien pull down lcdcs# pull up wake leave open rd# pull up smi# leave open wr# pull up usbrst# pull down lcdrdy leave open cd (0:7) pull down romcs (2:3)# pull up strobe# pull up cke pull down ack# pull up uucas# pull up busy pull down ulcas# pull up pe pull down mras (0:1)# pull up select pull down ucas# pull up autofeed# pull up lcas# pull up selectin# pull up ior# - error# pull up iow# - init# pull up reset - dir1284 leave open iocs16# - rxd pull down iochrdy - cts# pull up holdrq# leave open dsr# pull up holdak# pull up txd leave open sras# pull up rts# leave open scas# pull up dtr# leave open busrq (0:1)# pull up dcd# pull up busak (0:1)# leave open ri# pull up intrp leave open ps2clk pull up irq leave open ps2data pull up usbint# leave open gpio (0:23) pull down ps2int leave open excs (0:5)# leave open busclk pull up lcdbak leave open arbclksel pull down xin48m pull up dp (1:2) pull down xout48m leave open dn (1:2) pull down clkout48m leave open remark pins with no particular specification ( - ) cannot be left unconnected.
data sheet u14388ej2v0ds00 16 m m m m pd31172 2. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit power supply voltage v dd - 0.5 to +4.6 v v i < v dd + 0.5 v - 0.5 to +4.6 v input voltage v i v i < v dd + 3.0 v, dp (2:1), dn (2:1), ps2clk, ps2data pins - 0.5 to +6.6 v v o < v dd + 0.5 v - 0.5 to +4.6 v output voltage v o v o < v dd + 3.0 v, dp (2:1), dn (2:1), ps2clk, ps2data pins - 0.5 to +6.6 v operating ambient temperature t a - 40 to +85 c storage temperature t stg - 65 to +150 c cautions 1. do not simultaneously short multiple outputs. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions displayed in dc characteristics and ac characteristics in this section indicate the ranges in which normal operation and product quality can be guaranteed. capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min. max. unit input capacitance c i 8pf output capacitance c o1 8pf output capacitance note c o2 f = 1 mhz unmeasured pins returned to 0 v. 12 pf note applicable to dp (2:1), dn (2:1), ps2clk, and ps2data pins.
data sheet u14388ej2v0ds00 17 m m m m pd31172 dc characteristics (t a = - - - - 40 to +85 c, v dd = 3.3 0.3 v) (1) pins except for dp (2:1), dn (2:1) parameter symbol conditions min. max. unit output voltage, high v oh1 i oh = - 6 ma 2.4 v output voltage, low v ol1 i ol = 6 ma 0.4 v output voltage, high note 1 v oh2 i oh = - 9 ma 2.4 v output voltage, low note 1 v ol2 i ol = 9 ma 0.4 v output voltage, high note 2 v oh3 i oh = - 3 ma 2.4 v output voltage, low note 2 v ol3 i ol = 3 ma 0.4 v input voltage, high v ih1 2.0 v dd v input voltage, high note 2 v ih2 2.0 5.5 v input voltage, low v il 00.8v power supply current i dd 300 ma input leakage current i li v i = v dd , gnd 10 m a input leakage current, high i lih v i = v dd , arbclksel pin 141 m a output leakage current i lo v o = v dd , gnd 10 m a notes 1. applicable to sclk, ad (24:0), data (31:0), rd#, wr#, romcs (3:2)#, cke#, uucas#, ulcas#, mras (1:0)#, ucas#, lcas#, sras#, and scas# pins. 2. applicable to ps2clk and ps2data pins. (2) dp (2:1), dn (2:1) pins parameter symbol conditions min. max. unit output voltage, high v oh r l = 15 k w (connected to gnd) 2.8 3.6 v output voltage, low v ol r l = 1.5 k w (connected to v dd )0.3v differential input sensitivity v di 0.2 v differential common mode range v cm v di < 200 mv 0.8 2.5 v input voltage, high v ih_usb 2.0 v input voltage, low v il_usb 0.8 v remark refer to the usb specification, revision 1.0, for details.
data sheet u14388ej2v0ds00 18 m m m m pd31172 ac characteristics (t a = - - - - 40 to +85 c, v dd = 3.3 0.3 v) ac test input waveform 1.4 v all output pins v dd 0 v 1.4 v test points ac test output test points 1.4 v all output pins v dd 0 v 1.4 v test points
data sheet u14388ej2v0ds00 19 m m m m pd31172 load conditions (a) sclk, ad (0:24), data (0:31), rd#, wr#, romcs (2:3)#, clk#, uucas#, ulcas#, ulcas#, mras (0:1)#, ucas#, lcas#, sras#, scas# c l = 80 pf sclk, ad (0:24), data (0:31), rd#, wr#, romcs (2:3)#, clk#, uucas#, ulcas#, mras (0:1)#, ucas#, lcas#, sras#, scas# dut (b) dp (1:2), dn (1:2) in full-speed mode: c l = 50 pf in low-speed mode: c l = 350 pf dp (1:2), dn (1:2) dut (c) other output pins c l = 40 pf output pins (except for (a) and (b) above) dut
data sheet u14388ej2v0ds00 20 m m m m pd31172 (1) clock parameters parameter symbol conditions min. typ. max. unit xin48m clock frequency f clk 48.0 50.0 mhz (2) reset parameters parameter symbol conditions min. max. unit reset signal high-level width t rst 30 ns usbrst# signal low-level width t usbrst 30 ns (3) sdram interface parameters parameter symbol conditions min. max. unit sclk cycle t sclk 20.8 ns sclk high-level width t sclkh 8ns sclk low-level width t sclkl 8ns data output hold time t sdm 2ns data output delay time t sdo 15 ns data input setup time t sds 9.5 ns data input hold time t sdh 2ns t sclkh sclk (i/o) ad (24:0), wr#, romcs (3:2)#, uucas#, ulcas#, ucas#, lcas#, mras (1:0)#, sras#, scas#, cke (i/o) data (31:0) (output) data (31:0) (input) t sdm t sdo t sds t sdh hi-z hi-z t sclkl t sclk
data sheet u14388ej2v0ds00 21 m m m m pd31172 (4) system bus interface parameters (a) access to i/o area parameter symbol conditions min. max. unit command signal low-level width t clch 130 ns address setup time (to command signal) t avcl 10 ns address hold time (from command signal) t chav 10 ns iocs16# valid delay time t avcv 12 ns iocs16# floating delay time t avcz 10 ns data output hold time t dm 625ns data output delay time t do 30 ns data input setup time t ds1 10 ns data input setup time note t ds2 10 ns data input hold time t dh 10 ns note during 16550-compatible serial communication t avcl ad (24:0) (input) ior#/iow# (input) iocs16# (output) data (31:0) (input) data (31:0) (input) note data (31:0) (output) t chav t avcz t avcv t ds1 t dh t dh t ds2 t dm t do t clch note during 16550-compatible serial communication remark the broken lines indicate high impedance
data sheet u14388ej2v0ds00 22 m m m m pd31172 (b) access to lcd area parameter symbol conditions min. max. unit command signal low-level width t clch 90 ns address setup time (to command signal) t avcl 10 ns address hold time (from command signal) t chav 10 ns lcdrdy valid delay time t avrh 15 ns lcdrdy set delay time t clrl 12 ns lcdrdy floating delay time t avrz 10 ns data output hold time t dm 625ns data output delay time t do 30 ns data output valid time t dv 10 ns data input setup time t ds 10 ns data input hold time t dh 10 ns (i) when accessing the internal pci bus t avcl t clch t chav t avrz t clrl t avrh t dh t dm t dv ad (24:0) (input) lcdcs# (input) rd#/wr# (input) lcdrdy (output) data (31:0) (input) data (31:0) (output) t ds remark the broken lines indicate high impedance
data sheet u14388ej2v0ds00 23 m m m m pd31172 (ii) when accessing the configuration register of the pci host controller t avcl t chav t ds t dh t dm hi-z hi-z hi-z ad (24:0) (input) lcdcs# (input) rd#/wr# (input) lcdrdy (output) data (31:0) (input) data (31:0) (output) t clch t do
data sheet u14388ej2v0ds00 24 m m m m pd31172 (5) gpio parameters parameter symbol conditions min. max. unit gpio (23:0) output delay time t go 30 ns gpio (23:0) interrupt request generation time t gi 30 ns gpio (23:0) interrupt request clear time t gic 35 ns (a) in output mode t go gpio (23:0) (output) iow# (input) (b) in input mode t gic t gi t gi gpio (23:0) (input) irq (output) (level trigger interrupt) irq (output) (edge trigger interrupt) iow# (input) (edge interrupt request clear)
data sheet u14388ej2v0ds00 25 m m m m pd31172 (6) pcs (programmable chip select) parameters parameter symbol conditions min. max. unit excs output delay time t eo 30 ns t eo t eo ad (24:0) (i/o) excs (5:0)# (output) (7) pwm (pulse width modulation) parameters parameter symbol conditions min. max. unit lcdbak output delay time t lo 8 t sclk ns t lo lcdbak (output) note iow# (input) note high level: enable, low level: disable
data sheet u14388ej2v0ds00 26 m m m m pd31172 (8) ps/2 parameters parameter symbol conditions min. max. unit ps2clk clock high-level width t psch 3 t ns ps2clk clock low-level width t pscl 3 t ns ps2clk output delay time t pso t + 20 ns transmission start time t psgo 20 ns transmit data output delay time t psdo 3 t + 20 ns receive data setup time t psds 0ns receive data hold time t psdh 4 t ns receive disable setup time t psn 3 t ns remark t = 125 ns (cycle of internal clock for controlling ps/2) (a) transmission t pso t pso t pscl t psch ps2clk (i/o) iow# (input) ps2data (i/o) t psdo t psgo data0 data (1:7), parity bit stop bit start bit input input output input input output ps/2 interface enabled ps/2 interface disabled transmit data setting (b) reception t pscl ps2clk (i/o) ps2data (i/o) t psn t psdh t psds data0 data (1:7), parity bit stop bit start bit input output
data sheet u14388ej2v0ds00 27 m m m m pd31172 (9) 16550-compatible serial interface parameters parameter symbol conditions min. typ. max. unit transmit clock division ratio n 1 2 16 - 1 transmit clock rising edge delay time (from clk note 1 ) t bhd 10 ns transmit clock falling edge delay time (from clk note 1 ) t bld 15 ns n = 1 0.5clkc ns n = 2 1clkc ns n = 3 2clkc ns transmit clock pulse low-level width t lw n > 32clkcns n = 1 0.5clkc ns n = 2 1clkc ns n = 3 1clkc ns transmit clock pulse high-level width t hw n > 3(n - 2) clkc ns interrupt cancellation time (from ior# - , when reading lsr register) t rint1 40 ns interrupt cancellation time (from ior# , when reading rbr register) t rint2 30 ns sample clock delay time (from rclk) t scd 10 ns interrupt generation time (from valid data reception, reception error) t sint 1 rclkc + 20 note 2 ns interrupt cancellation time (from iow# , when writing to thr register) t hr 30 ns interrupt cancellation time (from ior# - , when reading iir register) t ir 40 ns transmission start time t irs 8 bauc 24 bauc + 20 ns interrupt generation time (from iow# - , when writing to thr register) t si 16 bauc 24 bauc + 20 ns interrupt generation time (from stop bit) t sti 8 bauc + 20 ns rts#, dtr delay time (from iow# - , when writing to mcr register) t mdo 30 ns interrupt cancellation time (from ior# , when reading msr register) t rim 30 ns interrupt cancellation time (from ri# - , cts#, dsr#, dcd#) t sim 30 ns notes 1. clk is the internal system clock of the 16550 serial controller, and has a frequency of 1.8462 mhz. 2. when bit 0 of the fcr register is 1, t sint = 3 rclkc + 20 (ns). during a timeout interrupt, t sint = 8 rclkc + 20 (ns). remark clkc: clk (internal system clock of 16550 serial controller) cycle rclkc: rclk (on-chip serial controller receive clock) cycle bauc: baudoutb (on-chip serial controller transmit clock) cycle rclkc = bauc in this case.
data sheet u14388ej2v0ds00 28 m m m m pd31172 (a) serial baudout timing t bhd t bld t bhd t bld t bld t bld clk (internal, 1.8462 mhz) baudoutb (1 cycle) (internal) baudoutb (2 cycles) (internal) baudoutb (3 cycles) (internal) baudoutb (n cycles, n > 3) (internal) t bhd t bhd t hw t lw t hw t hw t hw t lw t lw t lw (b) serial receive timing rclk (baudoutb) internal sample clock rxd (input) internal sample clock intrp (output) (receive data existence interrupt note 1 ) intrp (output) (receive status interrupt note 2 ) ior# (input) (reading rbr register) ior# (input) (reading lsr register) t sint t rint2 t scd 8 rclkc start bit stop bit parity bit data (5:8) 16 rclkc t rint1 notes 1. dependant on the existence of receive data. at this time, bit 0 of the ier register is 1, and bits 3 to 1 of the iir register are 0, 1, 0, respectively. 2. dependant on the receive line status. at this time, bit 2 of the ier register is 1, and bits 3 to 1 of the iir register are 0, 1, 1, respectively.
data sheet u14388ej2v0ds00 29 m m m m pd31172 (c) serial transmission timing rxd (input) iow# (input) (writing to thr register) ior# (input) (reading iir register) intrp note (output) t irs data (5:8) start bit parity bit start bit stop bit t sti t ir t hr t si t hr note dependant on whether the transmit buffer is empty. at this time, bit 1 of the ier register is 1, and bits 3 to 1 of the iir register are 0, 0, 1, respectively. (d) serial modem control timing iow# (input) (writing to mcr register) rts#, dtr# (output) cts#, dsr#, dcd# (input) intrp note (output) ior# (input) (reading msr register) ri# (input) t mdo t sim t sim t rim t rim t sim t mdo note dependant on the modem status. at this time, bit 3 of the ier register is 1, and bits 3 to 1 of the iir register are 0, 0, 0, respectively.
data sheet u14388ej2v0ds00 30 m m m m pd31172 (10) ieee1284-compliant parallel interface parameters (a) parallel port control signal output parameter symbol conditions min. max. unit parallel interface internal clock frequency t clk1284 24 mhz cd (7:0) output delay time (writing to data register) t 1 30 ns init#, strobe#, autofeed#, selectin# setup time t 2 4 t ns dir1284 setup time t 3 5 t ns remark t: parallel interface internal clock cycle (41.6 ns (min.)) iow# (input) cd (7:0) (i/o) dir1284 (output) init#, strobe#, autofeed#, selectin# (i/o) t 1 t 2 t 3 (b) compatible mode using fifo parameter symbol conditions min. max. unit cd (7:0) setup time t 4 24 t ns strobe# pulse width note 1 t 5 24 t ns busy response time t 6 12 t ns cd (7:0) hold time note 2 (from strobe# - ) t 7 24 t ns cd (7:0) hold time note 2 (from busy ) t 8 0ns strobe# setup time note 3 t 9 24 t ns notes 1. when there is no reaction from busy at a low level, strobe# continues to output a low level. 2. data is held while busy is high level. 3. when the fifo buffer is empty, this signal is held at a high level. remark t: parallel interface internal clock cycle (41.6 ns (min.)) strobe# (output) busy (input) t 4 t 5 valid data t 7 t 6 t 8 t 9 cd (7:0) (output)
data sheet u14388ej2v0ds00 31 m m m m pd31172 (c) during ecp normal-direction transfer parameter symbol conditions min. max. unit cd (7:0), autofeed# setup time t 10 1 t 2 t ns busy response time (from strobe# )t 11 0ns strobe# response time t 12 2 t 4 t ns busy response time (from strobe# - )t 13 0ns cd (7:0) hold time t 14 2 t 4 t ns strobe# setup time note t 15 3 t 6 t ns note when the fifo buffer is empty, this signal is held at a high level. remark t: parallel interface internal clock cycle (41.6 ns (min.)) strobe# (output) busy (input) t 10 valid data t 11 t 12 t 13 t 14 t 15 cd (7:0) autofeed# (output) (d) during ecp reverse-direction transfer parameter symbol conditions min. max. unit cd (7:0), busy setup time t 16 0ns autofeed# response time note (from ack# ) t 17 3 t ns ack# response time t 18 0ns autofeed# response time (from ack# - )t 19 5 t ns cd (7:0) hold time t 20 0ns ack# setup time t 21 0ns note when the fifo buffer is full, this signal is held at a low level. remark t: parallel interface internal clock cycle (41.6 ns (min.)) ack# (input) autofeed# (output) t 16 valid data t 17 t 18 t 19 t 20 t 21 cd (7:0) busy (input)
data sheet u14388ej2v0ds00 32 m m m m pd31172 (e) write timing in epp1.9 mode parameter symbol conditions min. max. unit iochrdy setup time t 22 3 t ns cd (7:0) output delay time t 23 30 ns strobe# setup time, dir1284 cancellation time (from iow# ) t 24 5 t ns strobe# setup time, dir1284 cancellation time (from busy ) t 25 4 t ns selectin#, autofeed# setup time (from strobe# , valid data output) t 26 0ns timeout generation time t 27 10 m s selectin#, autofeed# cancellation time (from iow# - ) t 28 3 t ns iochrdy cancellation time t 29 4 t ns cd (7:0) hold time t 30 1 t ns strobe# cancellation time, dir1284 setup time t 31 1 t ns remark t: parallel interface internal clock cycle (41.6 ns (min.)) ad (24:0), data (31:0) (input) iow# (input) valid data t 27 t 22 t 29 t 31 t 24 t 23 t 24 t 25 t 30 t 31 t 28 t 26 valid data iochrdy (output) strobe# (output) selectin# autofeed# (output) cd (7:0) (output) dir1284 (output) busy (input)
data sheet u14388ej2v0ds00 33 m m m m pd31172 (f) read timing in epp1.9 mode parameter symbol conditions min. max. unit iochrdy setup time t 32 3 t ns strobe# setup time, dir1284 cancellation time (from ior# ) t 33 5 t ns strobe# setup time, dir1284 cancellation time (from busy ) t 34 4 t ns selectin#, autofeed# setup time (from ior# ) t 35 6 t ns selectin#, autofeed# setup time (from dir1284 - ) t 36 30 ns timeout generation time t 37 10 m s selectin#, autofeed# cancellation time (from ior# - ) t 38 3 t ns cd (7:0) hold time t 39 0ns iochrdy cancellation time t 40 3 t ns strobe# cancellation time, dir1284 setup time t 41 1 t ns remark t: parallel interface internal clock cycle (41.6 ns (min.)) ad (24:0) (input) ior# (input) data (31:0) (output) iochrdy (output) strobe# (output) selectin# autofeed# (output) cd (7:0) (input) dir1284 (output) busy (input) t 34 t 36 t 38 t 39 t 32 t 40 valid data valid data hi-z hi-z hi-z hi-z t 37 t 33 t 41 t 35 t 33 t 41 t 34
data sheet u14388ej2v0ds00 34 m m m m pd31172 (g) write timing in epp1.7 mode parameter symbol conditions min. max. unit cd (7:0) output delay time t 42 30 ns strobe# setup time t 43 3 t ns selectin#, autofeed# setup time t 44 4 t ns iochrdy setup time t 45 3 t ns timeout generation time t 46 10 m s iochrdy cancellation time t 47 3 t ns selectin#, autofeed# cancellation time t 48 3 t ns strobe# cancellation time t 49 1 t ns cd (7:0) hold time t 50 30 ns remark t: parallel interface internal clock cycle (41.6 ns (min.)) ad (24:0), data (31:0) (input) iow# (input) cd (7:0) (output) iochrdy (output) strobe# (output) selectin# autofeed# (output) dir1284 (output) busy (input) t 43 t 44 t 49 t 50 t 42 valid data valid data t 48 t 45 t 47 t 46
data sheet u14388ej2v0ds00 35 m m m m pd31172 (h) read timing in epp1.7 mode parameter symbol conditions min. max. unit dir1284 setup time t 51 3 t ns selectin#, autofeed# setup time t 52 30 ns iochrdy setup time t 53 3 t ns timeout generation time t 54 10 m s iochrdy cancellation time t 55 3 t ns selectin#, autofeed# cancellation time t 56 3 t ns cd (7:0) hold time t 57 0ns dir1284 cancellation time t 58 1 t ns remark t: parallel interface internal clock cycle (41.6 ns (min.)) ad (24:0) (input) ior# (input) data (31:0) (output) iochrdy (output) strobe# (output) selectin# autofeed# (output) cd (7:0) (input) dir1284 (output) busy (input) t 57 t 58 valid data hi-z hi-z valid data hi-z hi-z t 52 t 56 t 51 t 53 t 55 t 54
data sheet u14388ej2v0ds00 36 m m m m pd31172 (i) interrupt request timing parameter symbol conditions min. max. unit interrupt request setup time t 59 4 t ns interrupt request generation time (from ack# - , error# ) t 60 3 t ns interrupt request cancellation time (from iow# - )t 61 5 t ns interrupt request cancellation time note (from ior# - ) t 62 3 t ns interrupt request generation time (from iow# - )t 63 5 t ns note when bit 7 of the cnfga register = 0 remark t: parallel interface internal clock cycle (41.6 ns (min.)) iow# (input) ior# (input) ack# (input) intrp, irq (output) t 60 t 61 t 60 t 62 t 63 t 59 error# (input) t 60 t 60
data sheet u14388ej2v0ds00 37 m m m m pd31172 (11) usb interface applicable to the dp (2:1) and dn (2:1) pins. refer to the usb specification, revision 1.0, for details. parameter symbol conditions min. max. unit rise time t r c l = 50 pf 4 20 ns fall time t f c l = 50 pf 4 20 ns t r , t f matching t rfm t r /t f 90 110 % full-speed mode differential output signal crossover point v crs 1.3 2.0 v c l = 50 pf 75 ns rise time t r c l = 350 pf 300 ns c l = 50 pf 75 ns fall time t f c l = 350 pf 300 ns t r , t f matching t rfm t r /t f 80 120 % low-speed mode differential output signal crossover point v crs 1.3 2.0 v impedance imp. 28 43 w 90% 90% 10% v crs t f t r 10% dp (2:1), dn (2:1)
data sheet u14388ej2v0ds00 38 m m m m pd31172 3. package drawing 208-pin plastic fbga (15x15) outline drawings item millimeters d d1 14.4 15.00 0.10 e 15.00 0.10 e1 14.4 b 0.50 x 0.08 y 0.10 y1 0.20 zd 1.1 ze 1.1 + 0.05 - 0.10 w 0.20 e 0.80 a 1.51 0.15 a1 0.35 0.10 a2 1.16 p208s1-80-2c x index mark w w ze zd y1 y e a1 a2 a sb sa s s sab m f 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pn m lkjhgfedcba 25 a b s d d1 e1 e r t u 15 16 17 4 C r0.3 4 C c1.0 208 C b f
data sheet u14388ej2v0ds00 39 m m m m pd31172 4. recommended soldering conditions the m pd31172 should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 4-1. surface mounting type soldering conditions soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) ir35-107-3 vps package peak temperature: 215c, time: 25 to 40 seconds (at 200c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) vp15-107-3 partial heating pin temperature: 300c max., time: 3 seconds max. (per pin row) C note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
data sheet u14388ej2v0ds00 40 m m m m pd31172 [memo]
data sheet u14388ej2v0ds00 41 m m m m pd31172 [memo]
data sheet u14388ej2v0ds00 42 m m m m pd31172 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
data sheet u14388ej2v0ds00 43 m m m m pd31172 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1
m m m m pd31172 related documents: v rc 4172 users manual (u14386e) v r 4121 users manual (u13569e) v r 4121 data sheet (u14691e) reference materials: electrical characteristics for microcomputer (iei-601) the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. v r 4121 and v rc 4172 are trademarks of nec corporation. windows is either a registered trademark or trademark of microsoft corporation in the united states and/or other countries. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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